This invention relates to semiconductor devices having self-aligned metallization to the exposed silicon regions of the device, and to a process for forming such metallization by the selective deposition of tungsten.
The continuing trend toward decreased size and increased packing density of integrated circuit devices demands increasing sophistication in the design and fabrication of these devices and circuits.
In VLSI (very large scale integration) circuits, mask alignment and etching tolerance requirements of conventional fabrication techniques has limited the packing density of both active devices and interconnect lines. The development of self-aligned contacts to the source, drain and polysilicon gate and interconnect lines in MOS (metal oxide semiconductor) devices has thus allowed increased packing densities of the devices and interconnects.
Self-aligned contacts are those in which enlarged contact areas are provided to allow for non-critical alignment tolerance, without increasing the device size.
One approach to the achievement of self-aligned contacts for MOS devices is to combine polysilicon contact (PC) and gate (G) masks to define the self-aligned contacts. See M. K. Kahn et al "A Self-Aligned Contact (SAC) Process For Manufacturing VLSI Circuits", 1979 ECS Meeting, Los Angeles, CA., Abstract No. 548, page 1469.
Another approach to the achievement of self-aligned contacts is to form a polysilicon layer directly on the source, drain and gate regions of the MOS device, and then form isolations in this polysilicon layer by the selective oxidation of the layer using a non-critical silicon nitride mask. H. S. Fu et al, "A New MOS Transistor With Self-Registering Source-Drain and Gate Contacts", IEDM, 1980, page 140.
Another limitation encountered in the design of VLSI circuits is the electrical resistance of the polysilicon gates and interconnects. It is known to lower the electrical resistivity of these structures by the partial or total replacement of polysilicon by metal silicides. See, for example, B. Crowder et al, "One Micrometer MOSFET VLSI Technology: Part VII-Metal Silicide Interconnection Technology-A Future Perspective", IEEE Journal of Solid State Circuits, SC-14, No. 2, April 1979, page 291. The ability to selectively form silicides on single crystal silicon and polysilicon has been employed to form low resistivity refractory metal silicide interconnects self-aligned to the source, drain and gate regions of MOS devices. C. K. Lau et al, "Titanium Disilicide Self-Aligned Source/Drain+Gate Technology", IEDM, 1982, page 714.
In a refinement of the above technique, silicide was additionally extended over the field oxide region by forming an amorphous silicon layer on the refractory metal layer over the insulating field oxide region, using a non-critical photomasking step to form the silicon layer, prior to formation of the silicide by reaction of the refractory metal in contact with the silicon. The resultant extension of the silicide interconnect over the field oxide region, allows source and drain contacts to be located adjacent to the source and drain regions rather than directly over them, enabling a relaxation of mask alignment and etching tolerance requirements. D. C. Chen et al, "A New Device Interconnect Scheme For Sub-Micron VLSI", IEDM, 1984, page 118.
However, the above-described technique requires additional steps of deposition, masking and etching to form the amorphous silicon pattern, heating to form the silicide, and etching to remove the unreacted refractory metal after silicide formation. In addition, since the silicide is not effective to prevent cross-diffusion between subsequently formed aluminum contacts and the underlying silicon, a separate layer of a barrier material such as titanium nitride or tungsten must be formed on the silicide interconnect layer in any via holes which extend beyond the edge of the field oxide into an island region of the device.
Accordingly, it is an object of the invention to provide a self-aligned metallization for a semiconductor device which has lower electrical resistivity than the polysilicon and silicide interconnects of the prior art.
It is another object of the invention to provide such a self-aligned metallization over the insulating regions of the device without the necessity for forming a silicide and without an additional etching step to remove unreacted refractory metal from the surface of the insulating regions.
It is still another object of the invention to provide such a self-aligned metallization which does not require the formation of an additional diffusion barrier layer over the metallization in those contact areas which extend beyond the edge of the insulating regions into an island region of the device.